#include <stdio.h>
#include <stdlib.h>
#include "common.h"
#include "scu_reg.h"
#include "printf.h"
#include "inno_lpddr4_1600.h"
//***********************************************************//
// resnet50_imagenet testcase
//***********************************************************//

// TODO: config base address
#define   AXI_LITE_BASE_ADDR  0x35000000 //0xa0000000 // variable you need to config
#define   INST_BASE_ADDR      0x80100000 // variable you need to config
#define   IMAGE_BASE_ADDR     0x80200000 // variable you need to config
#define   WEIGHT_BASE_ADDR    0x90000000 // variable you need to config

//***********************************************************//
// the offset address of npu registers
#define REG_ADDR_START             0x8
#define REG_ADDR_INT               0x10
#define REG_ADDR_INT_MASK          0x14
#define REG_ADDR_INSTR_BASE        0x18   // 64-bit
#define REG_ADDR_IMG_BASE          0x20   // 64-bit
#define REG_ADDR_WGT_BASE          0x28   // 64-bit
#define REG_ADDR_PROF_SYST_BASE    0xC00  // 64-bit
#define REG_ADDR_PROF_LOAD_BASE    0xC08  // 64-bit
#define REG_ADDR_PROF_SAVE_BASE    0xC10  // 64-bit
#define REG_ADDR_PROF_CONV_BASE    0xC18  // 64-bit
#define REG_ADDR_PROF_MISC_BASE    0xC20  // 64-bit
#define REG_ADDR_ERR_CODE          0x400  // 64-bit
#define REG_ADDR_INST_CODE         0x404  // 64-bit

#define baseaddr                   0x37010000

#define D2D_AXI_BASE                  0x680000000
//***********************************************************//
#define     D2D_BASE                  0x37010000      //X1_APB SLAVE1

#define     TOP_AI_CHOOSE             0x60001000

#define     ADDR_CONFIG7                          D2D_BASE+0x101c
            //b31      ,  bypass_mode ENABLE 1'b1
            //b30      ,  flit_init_para  1'b0
            //b28:b21  ,  prbs_type 8'b0
            //b20      ,  prbs_mode 1'b0


#define     ADDR_SHIFT                            D2D_BASE+0x1020
            //b16      ,  syn_hdr_pattern_mode 1'b1
            //b15:b0   ,  shift_mode 16'b0


#define     ADDR_CONFIG_wr_start                  D2D_BASE+0x2054
            //b31:b0  ,  0x1010_0000


#define     ADDR_CONFIG_wr_end                    D2D_BASE+0x2058
            //b31:b0  ,  0x1010_8000


#define     ADDR_CONFIG_rd_start                  D2D_BASE+0x205c
            //b31:b0  ,  0x1011_0000

#define     ADDR_CONFIG_rd_end                    D2D_BASE+0x2060
            //b31:b0  ,  0x1011_8000


#define     ADDR_SOFT_RST                         D2D_BASE+0x5000
            //b0,  SOFT_RST 1'b1 RST

#define     ADDR_INTR_CLEAR                       D2D_BASE+0x900c
            //b0,  1'b1 INTR_CLEAR



#define     ADDR_INTR                             D2D_BASE+0x9004
            //b0,  1'b1 Read INTR

#define     ADDR_INTR_REG                         D2D_BASE+0x9008
            //b0,  1'b1 bypass_rd_valid
            //b11,  1'b1 error

#define     ADDR_SYS_ENABLE                       D2D_BASE+0x9010
            //b0,  1'b1 on 1'b0 off

//***********************************************************//
int main()
{

    long addr_src;
    long addr_dst;
    long data64;
    long addr;
    int  data;
    //int  result;
    int  i,j;
    int  ret_value ;
    int  test_len=0x01000; //
    //***********************************************************//
    // config image & weight @ instructions base address
    const uint32_t total_io_size  = 757760;
    const uint32_t total_wgt_size = 25609600;
    const uint32_t total_inst_bin_size = 114868;
    const uint32_t total_prof_size = 65360;
    const uint32_t total_ddr_size = 26547588;

    uint32_t image_base_addr = IMAGE_BASE_ADDR  ;
    uint32_t wgt_base_addr   = WEIGHT_BASE_ADDR ;//image_base_addr + total_io_size + 0x100000;
    uint32_t instr_base_addr = INST_BASE_ADDR   ;//wgt_base_addr + total_wgt_size + 0x100000;
    uint32_t result ;//wgt_base_addr + total_wgt_size + 0x100000;

    //***********************************************************//
    // 1. 鍔犺浇 image 鍒板湴鍧� image_base_addr + 0x100000
    // 2. 鍔犺浇 weight 鍒板湴鍧� wgt_base_addr + 0x100000
    // 3. 鍔犺浇鎸囦护鍒板湴鍧� instr_base_addr

    //***********************************************************//
    uint32_t 	    SystemAPBClock = 20000000;
//    uart0_init(0xA);
//   // uart0_putchar(0x55);
//    printf("============hello world!====================");
//    printf("\n");
    //PLL0 Analog 600M  PLL1 1000M
//    			*((volatile uint32_t *) (baseaddr)) = 0x0; //change to ref
//    			*((volatile uint32_t *) (baseaddr + 0x20)) |= (0x3UL << 1); //reset pll0 pll1
//    			*((volatile uint32_t *) (baseaddr + 0x2c)) &= ~(1 << 5); //disable pll0
//    			*((volatile uint32_t *) (baseaddr + 0x30)) &= ~(1 << 5); //disable pll1
//    			*((volatile uint32_t *) (baseaddr + 0x2c)) &= (0xffffe0fc); //clean pll0 div_ctrl
//    			*((volatile uint32_t *) (baseaddr + 0x2c)) |= (0 << 8) ; //pll0 600M ([12:8] -> 20 * (30 + div_ctrl))
//    			*((volatile uint32_t *) (baseaddr + 0x20)) = (0x0);//dereset pll0 pll1
//    			*((volatile uint32_t *) (baseaddr + 0x2c)) |= (1 << 5); //enable pll0
//    			*((volatile uint32_t *) (baseaddr + 0x30)) |= (1 << 5); //enable pll1
//    			*((volatile uint32_t *) (baseaddr + 0x48)) = 0xeee000e; //config REG_CLK_CFG
//    			SystemAPBClock = 300000000;
//    			uart0_init(0xA2);
//    			printf("Hello World 600M!!!");
//    			printf("\n");

    		    //PLL0 Analog 1000M  PLL1 1000M

    			*((volatile uint32_t *) (baseaddr)) = 0x0; //change to ref
    			*((volatile uint32_t *) (baseaddr + 0x20)) |= (0x3UL << 1); //reset pll0 pll1
    			*((volatile uint32_t *) (baseaddr + 0x2c)) &= ~(1 << 5); //disable pll0
    			*((volatile uint32_t *) (baseaddr + 0x30)) &= ~(1 << 5); //disable pll1
    			*((volatile uint32_t *) (baseaddr + 0x2c)) &= (0xffffe0ff); //clean pll0 div_ctrl
    			*((volatile uint32_t *) (baseaddr + 0x2c)) |= (0 << 8); //pll0 600M ([12:8] -> 20 * (30 + div_ctrl))
    			*((volatile uint32_t *)(baseaddr + 0x20)) = (0x0);//dereset pll0 pll1
    			*((volatile uint32_t *) (baseaddr + 0x2c)) |= (1 << 5); //enable pll0
    			*((volatile uint32_t *) (baseaddr + 0x30)) |= (1 << 5); //enable pll1
    			*((volatile uint32_t *) (baseaddr + 0x48)) = 0x0000000; //config REG_CLK_CFG 0xeee000e;
    			SystemAPBClock = 500000000;
    			uart0_init(0x21);
    			printf("Hello World 1000M!!!");
    			printf("\n");
    			ddr_config_1600();

    			//  config_data0~27 + end  + shift + wr/rd srart end  (28 + 1 + 1 + 4 )
    			// tx rx write lane0-7

    			write(baseaddr+0x3000,  0x031181f1);

    			write(baseaddr+0x3004,  0x01d4006f);

    			write(baseaddr+0x3008,  0x018a8231);

    			write(baseaddr+0x300c,  0x00040000);


    			write(baseaddr+0x3100,  0x0315c201);//PD_DAC_lane1==1'b1

    			write(baseaddr+0x3104,  0x01dd0000);//PD_BUFFER_lane1==1'b1

    			write(baseaddr+0x3108,  0x018a8231);

    			write(baseaddr+0x310c,  0x0a740000);

    			write(baseaddr+0x3110,  0x4104000);

    			write(baseaddr+0x3114,  0x4110000);



    			write(baseaddr+0x3200,  0x0311c201);

    			write(baseaddr+0x3204,  0x01de0000);//PD_BUFFER_lane2=1

    			write(baseaddr+0x3208,  0x018a8231);

    			write(baseaddr+0x320c,  0x0a740000);

    			write(baseaddr+0x3210,  0x4104000);

    			write(baseaddr+0x3214,  0x4110000);


    			write(baseaddr+0x3300,  0x0311c201);

    			write(baseaddr+0x3304,  0x001c0000);//SLICER_BUFFER_CTRL_lane3==0000

    			write(baseaddr+0x3308,  0x018a8231);

    			write(baseaddr+0x330c,  0x00040002);

    			write(baseaddr+0x3310,  0x4104000);

    			write(baseaddr+0x3314,  0x4110000);


    			write(baseaddr+0x3400,  0x0311c201);

    			write(baseaddr+0x3404,  0x01dd0000);

    			write(baseaddr+0x3408,  0x018a8231);

    			write(baseaddr+0x340c,  0x0a740000);

    			write(baseaddr+0x3410,  0x4104000);

    			write(baseaddr+0x3414,  0x4110000);



    			write(baseaddr+0x3500,  0x03011201);//PD_RX_TEST_BUFFER_lane5=0

    			write(baseaddr+0x3504,  0x01de0000);//PD_BUFFER_lane5=1

    			write(baseaddr+0x3508,  0x018a8231);

    			write(baseaddr+0x350c,  0x0a740000);

    			write(baseaddr+0x3510,  0x4104000);

    			write(baseaddr+0x3514,  0x4110000);



    			write(baseaddr+0x3600,  0x0311c201);

    			write(baseaddr+0x3604,  0x01dc0000);//PD_BUFFER_lane6==0

    			write(baseaddr+0x3608,  0x018a8231);

    			write(baseaddr+0x360c,  0x0a740000);

    			write(baseaddr+0x3610,  0x4104000);

    			write(baseaddr+0x3614,  0x4110000);


    			write(baseaddr+0x3700,  0x0301c201);//PD_RX_TEST_BUFFER_lane7=0

    			write(baseaddr+0x3704,  0x01de0000);//PD_BUFFER_lane7=1

    			write(baseaddr+0x3708,  0x018a8231);

    			write(baseaddr+0x370c,  0x0a740000);

    			write(baseaddr+0x3710,  0x4104000);

    			write(baseaddr+0x3714,  0x4110000);



    			write(baseaddr+0x7000,  0x6dd06390);//RX_IBIAS_CMLCMOS_CTRL=1010  RX_CML_TO_CMOS_DRIVER_CTRL==011

    			write(baseaddr+0x7004,  0x53800101);//4 modify



                write(baseaddr+0x700c,  0x0002014b);//PLL  pll_div=10100 CLK_SOURCE==0 pll_rst=0

    			write(baseaddr+0x7010,  0x0101010d);
    			read(baseaddr+0x7014);//com_bgr_reday=1 rx_bgr_reday=1 32'h30000

    			write(baseaddr+0x7018,  0x20820820);

    			write(baseaddr+0x701c,  0x20820820);


    			write(baseaddr+0x8000,  0xff);

    			write(baseaddr+0x8000,  0xff);


    			write(baseaddr+0x8000,  0x0);



    			write(baseaddr+0x8004,  0xff);

    			write(baseaddr+0x8004,  0xff);

    			write(baseaddr+0x8004,  0x0);




    			write(baseaddr+0x8004,  0xff);

    			write(baseaddr+0x8004,  0xff);

    			write(baseaddr+0x8004,  0xff);

    			write(baseaddr+0x8004,  0xff);

    			write(baseaddr+0x8004,  0xff);

    			write(baseaddr+0x8004,  0xff);

    			write(baseaddr+0x8004,  0x0);






    			write(baseaddr+0x1000,  0x001233ff);

    			write(baseaddr+0x9010,  0x1);

    			write(baseaddr+0x1004,  0x00032000);

    			write(baseaddr+0x1008,  0xfff00000);

    			write(baseaddr+0x100c,  0xf82fffff);

    			write(baseaddr+0x1010,  0xea504020);

    			write(baseaddr+0x1014,  0xea0c03e8);

    			write(baseaddr+0x1018,  0xea1c0000);


    			write(baseaddr+0x1020,  0x10000);

    			write(baseaddr+0x101c,  0x80000000);//prbs bypass
    			write(baseaddr+0x101c,  0x80000000);//prbs bypass



    			write(baseaddr+0x101c,  0x80300000);//prbs

    		/*	write(baseaddr+0x101c,  0x0);//prbs

    			write(baseaddr+0x101c,  0x300000);//prbs

    			write(baseaddr+0x101c,  0x0);//prbs

    			write(baseaddr+0x101c,  0x300000);//prbs

    			write(baseaddr+0x101c,  0x0);//prbs


    			write(baseaddr+0x5000,  0x1);

    			write(baseaddr+0x101c,  0x300000);//prbs

    			write(baseaddr+0x101c,  0x0);//prbs*/


    				result = read(baseaddr+0x6028);//prbs_error_counter_lane0

    			    printf("prbs_error_lane0 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6028);//prbs_error_counter_lane0

    			    printf("prbs_error_lane0 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6034);//prbs_error_counter_lane3
    			    printf("prbs_error_lane3 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6028);//prbs_error_counter_lane0

    			    printf("prbs_error_lane0 : %x", result);
    			    printf("\n");


    				result = read(baseaddr+0x6038);//prbs_error_counter_lane4
    			    printf("prbs_error_lane4 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6038);//prbs_error_counter_lane4
    			    printf("prbs_error_lane4 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6038);//prbs_error_counter_lane4
    			    printf("prbs_error_lane4 : %x", result);
    			    printf("\n");


    				result = read(baseaddr+0x6038);//prbs_error_counter_lane4
    			    printf("prbs_error_lane4 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6028);//prbs_error_counter_lane0

    			    printf("prbs_error_lane0 : %x", result);
    			    printf("\n");


    				result = read(baseaddr+0x603c);//prbs_error_counter_lane5
    			    printf("prbs_error_lane5 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6028);//prbs_error_counter_lane0

    			    printf("prbs_error_lane0 : %x", result);
    			    printf("\n");



        			write(baseaddr+0x101c,  0x80000000);//prbs

    				result = read(baseaddr+0x6028);//prbs_error_counter_lane0
    			    printf("prbs_error_lane0 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6028);//prbs_error_counter_lane0
    			    printf("prbs_error_lane0 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6038);//prbs_error_counter_lane4
    			    printf("prbs_error_lane4 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6038);//prbs_error_counter_lane4
    			    printf("prbs_error_lane4 : %x", result);
    			    printf("\n");


        			write(baseaddr+0x101c,  0x80300000);//prbs

    				result = read(baseaddr+0x6028);//prbs_error_counter_lane0
    			    printf("prbs_error_lane0 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6028);//prbs_error_counter_lane0
    			    printf("prbs_error_lane0 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6038);//prbs_error_counter_lane4
    			    printf("prbs_error_lane4 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6038);//prbs_error_counter_lane4
    			    printf("prbs_error_lane4 : %x", result);
    			    printf("\n");






        			write(baseaddr+0x8004,  0xff);//RX 8条lane 复位

        			write(baseaddr+0x8004,  0x0);

    				result = read(baseaddr+0x6028);//prbs_error_counter_lane0

    			    printf("prbs_error_lane0 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6038);//prbs_error_counter_lane4
    			    printf("prbs_error_lane4 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6038);//prbs_error_counter_lane4
    			    printf("prbs_error_lane4 : %x", result);
    			    printf("\n");


        			write(baseaddr+0x8000,  0xff);//TX 8条lane 复位

        			write(baseaddr+0x8000,  0x0);

        			write(baseaddr+0x8004,  0xff);//RX 8条lane 复位

        			write(baseaddr+0x8004,  0x0);

    				result = read(baseaddr+0x602c);//prbs_error_counter_lane1
    			    printf("prbs_error_lane1 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6030);//prbs_error_counter_lane2
    			    printf("prbs_error_lane2 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6028);//prbs_error_counter_lane0

    			    printf("prbs_error_lane0 : %x", result);
    			    printf("\n");

        			write(baseaddr+0x8004,  0xff0000ff);

        			write(baseaddr+0x8004,  0xff000000);//RX 8条lane 比特翻转

    				result = read(baseaddr+0x6028);//prbs_error_counter_lane0

    			    printf("prbs_error_lane0 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6038);//prbs_error_counter_lane4
    			    printf("prbs_error_lane4 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6038);//prbs_error_counter_lane4
    			    printf("prbs_error_lane4 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6034);//prbs_error_counter_lane3
    			    printf("prbs_error_lane3 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6038);//prbs_error_counter_lane4
    			    printf("prbs_error_lane4 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x603c);//prbs_error_counter_lane5
    			    printf("prbs_error_lane5 : %x", result);
    			    printf("\n");

    			 	result = read(baseaddr+0x6040);//prbs_error_counter_lane6
    			    printf("prbs_error_lane6 : %x", result);
    			    printf("\n");

    				result = read(baseaddr+0x6044);//prbs_error_counter_lane7
    			    printf("prbs_error_lane7 : %x", result);
    			    printf("\n");








    			  write(ADDR_CONFIG7,0x80000000);

    			  write(ADDR_CONFIG_wr_start,0x10100000);
    			  write(ADDR_CONFIG_wr_end,  0x10108000);
    			  write(ADDR_CONFIG_rd_start,  0x10110000);
    			  write(ADDR_CONFIG_rd_end,  0x10118000);
    			  write(ADDR_SOFT_RST,  0x00000000);
    			  write(ADDR_SYS_ENABLE,  0x00000001);




    			   write(D2D_AXI_BASE + 0x10100000 ,0x12345678);

    			   result = read(D2D_AXI_BASE + 0x10100000 );
    			    printf("D2D Write : %x", result);

    			    result = read(D2D_AXI_BASE + 0x10110000 );
    			    printf("D2D READ : %x", result);

    			    /*addr_src =  0x80000000;//0x10080000;// source address
    			    addr_dst =  0x10100000;//0x100b0000;// destination address
    			    //addr_dst =  0x80008000;//0x100b0000;// destination address
    			   printf_msg("------------writing over, config the dmac------------");

    			    //Enable DMAC, Interrupt enabled as well
    			    write(DMAC_CFGREG,0x00000003); //Int_En, DMAC_En

    			    //CH1_CFGREG
    			    data64 = ( (0b00       << 0 )
    			              |(0b00       << 2 )
    			              |(0b0000     << 18)  //READ-CH unique ID
    			              |(0b0000     << 25)  //WRITE-CH unique ID
    			             );
    			    write(CH1_CFG,data64);
    			    write(CH1_CFG+4,0x0 );        //TT_FC
    			    //CH1_SAR
    			    write(CH1_SAR,addr_src);
    			    //CH1_DAR
    			    write(CH1_DAR,addr_dst);
    			    //CH1_BLOCK_TS
    			    write(CH1_BLOCK_TS,0x7f);  //64 beats
    			    //CH1_CTL
    			    data64 = ( (0b101      << 8 )  //256bit,SRC_TR_WIDTH
    			              |(0b101      << 11)  //256bit,DST_TR_WIDTH
    			              |(0b01     << 14)  //8,Source Burst Lenth
    			              |(0b01     << 18)  //8,Destin Burst Lenth
    			             );
    			    write(CH1_CTL,data64);  //32 beats
    			    data64 = (0b1 << (58-32));     //CH1_CTL[58]
    			    write(CH1_CTL+4,data64);

    			    //Enable Status
    			    write(CH1_INTSTATUS_ENABLEREG,0x1);

    			    //Enable channel[1]
    			    write(DMAC_CHENREG,0x00000101);
    			    data = read(DMAC_CHENREG);
    			    printf_msg("DMAC_CHENREG is : =%x  \n",data );

    			    //waiting for end
    			    do {
    			        data64 =  read(CH1_INTSTATUS);
    			        data64 =  data64 & 0x00000001;//0x2
    			      } while(data64==0);
    			    printf_msg("DMAC_CHENREG is : =%x\n ",data64 );
    			    printf_msg("------------transfer over, start read------------");//*********************

    			  data=read(ADDR_INTR_REG);
    			  printf_msg("ADDR_INTR_REG is : =%x\n ",data );

    			    addr_src =  0x10110000;//0x10080000;// source address
    			    addr_dst =  0x80008000;//0x100b0000;// destination address

    			   printf_msg("------------writing over, config the dmac------------");

    			    //Enable DMAC, Interrupt enabled as well
    			    write(DMAC_CFGREG,0x00000000); //Int_En, DMAC_En
    			    write(DMAC_CFGREG,0x00000003); //Int_En, DMAC_En

    			    //CH1_CFGREG
    			    data64 = ( (0b00       << 0 )
    			              |(0b00       << 2 )
    			              |(0b0000     << 18)  //READ-CH unique ID
    			              |(0b0000     << 25)  //WRITE-CH unique ID
    			             );
    			    write(CH1_CFG,data64);
    			    write(CH1_CFG+4,0x0 );        //TT_FC
    			    //CH1_SAR
    			    write(CH1_SAR,addr_src);
    			    //CH1_DAR
    			    write(CH1_DAR,addr_dst);
    			    //CH1_BLOCK_TS
    			    write(CH1_BLOCK_TS,0x7f);  //64 beats
    			    //CH1_CTL
    			    data64 = ( (0b101      << 8 )  //256bit,SRC_TR_WIDTH
    			              |(0b101      << 11)  //256bit,DST_TR_WIDTH
    			              |(0b01     << 14)  //8,Source Burst Lenth
    			              |(0b01     << 18)  //8,Destin Burst Lenth
    			             );
    			    write(CH1_CTL,data64);  //32 beats
    			    data64 = (0b1 << (58-32));     //CH1_CTL[58]
    			    write(CH1_CTL+4,data64);

    			    //Enable Status
    			    write(CH1_INTSTATUS_ENABLEREG,0x1);

    			    //Enable channel[1]
    			    write(DMAC_CHENREG,0x00000101);
    			    data = read(DMAC_CHENREG);
    			    printf_msg("DMAC_CHENREG is : =%x  \n",data );

    			    //waiting for end
    			    do {
    			        data64 =  read(CH1_INTSTATUS);
    			        data64 =  data64 & 0x00000001;//0x2
    			      } while(data64==0);
    			    printf_msg("DMAC_CHENREG is : =%x\n ",data64 );
    			    printf_msg("------------transfer over, start compare------------");



    			    ret_value = 0;
    			    addr_src = 0x80000000;
    			    addr_dst = 0x80008000;
    			    for(i=0;i<test_len;i=i+32)  {
    			      data64 = read(addr_src);
    			      data64 = data64 - read(addr_dst);
    			      if(data64==0) {
    			        addr_src = addr_src+64;
    			        addr_dst = addr_dst+32;
    			         printf_msg("addr_src is : =%d\n",addr_src );
    			      }
    			      else {
    			        ret_value = 1;
    			        printf_msg("error happens, current_address is : src=%x , dst=%x", addr_src, addr_dst);
    			        break;
    			      }
    			    }
    			    print_flag(ret_value);*/



    return 0;
}

